Test MP+dmb.sy+pos-[fr-rf]-ctrl-addr-pos

AArch64 MP+dmb.sy+pos-[fr-rf]-ctrl-addr-pos
"DMB.SYdWW Rfe PosRR FrLeave RfBack DpCtrldR DpAddrdR PosRR Fre"
Cycle=Rfe PosRR FrLeave RfBack DpCtrldR DpAddrdR PosRR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpAddrdR DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR FrLeave RfBack DpCtrldR DpAddrdR PosRR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X5=z; 1:X8=x;
2:X1=y;
}
 P0          | P1                  | P2          ;
 MOV W0,#1   | LDR W0,[X1]         | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]         | STR W0,[X1] ;
 DMB SY      | LDR W3,[X1]         |             ;
 MOV W2,#1   | CBNZ W3,LC00        |             ;
 STR W2,[X3] | LC00:               |             ;
             | LDR W4,[X5]         |             ;
             | EOR W6,W4,W4        |             ;
             | LDR W7,[X8,W6,SXTW] |             ;
             | LDR W9,[X8]         |             ;
Observed
    y=1; x=1; 1:X9=0; 1:X7=1; 1:X3=1; 1:X2=2; 1:X0=2;
and y=1; x=1; 1:X9=1; 1:X7=1; 1:X3=2; 1:X2=0; 1:X0=2;
and y=1; x=1; 1:X9=1; 1:X7=1; 1:X3=1; 1:X2=0; 1:X0=2;
and y=1; x=1; 1:X9=1; 1:X7=1; 1:X3=1; 1:X2=0; 1:X0=1;